Ion implantation process is used in manufacturing electrical and optical devices. It is a process by which dopants or impurities are introduced into a target to alter the target's mechanical, electrical, and/or optical property. In integrated circuit (IC) device manufacturing, the target may be silicon or other semiconductor wafers, or one or more features or films thereon. Generally, the dopants or impurities may have one or more properties that differ from the properties of the target. Once implanted into a region in the target, the dopants or impurities may alter the region's properties.
During the ion implantation process, the target or the wafer 102 may be supported on a platen 112. As illustrated in FIG. 1, the platen 112 may comprise one or more electrodes 114 that are electrically connected to a power supply 116. In some embodiments, multiple concentric electrodes 114 are provided where one of the electrodes may be an inner electrode 114a and another electrode may be an outer electrode 114b. In other embodiments, multiple electrodes are provided at opposite sides of the platen 112. To electrostatically clamp the wafer 102 onto the platen, the bias voltage may be applied to the electrodes 114. In some embodiments, opposite voltage may be applied to different electrodes. For example, one of the electrodes 114 may be applied with positive voltage, whereas negative voltage is applied to another electrode 114. The magnitude of the clamping voltage may be the same or different.
Referring to FIG. 2, there is shown timing of the clamping voltage provided from the power supply 116 to one or more electrodes 114 in the platen 112. After the wafer 102 is loaded onto the platen 112, clamping voltage (V1) is applied to the electrodes 114 at T1 and the wafer 102 is electrostatically clamped onto the platen 112. Although not illustrated, those skilled in the art will recognize that if two or more electrodes are provided, one of the electrodes will be applied positive V1 and the other electrode will be applied with negative V1. The voltage applied to the electrodes 114 may be maintained during the ion implantation process, and the wafer 102 may remain clamped on the platen 112. After the ion implantation is completed (i.e. T2), the clamping voltage V1 is no longer applied to the electrodes 114, and the wafer 102 is removed from the platen 112. In some embodiments, the wafer 102 removal process may include lifting and separating the wafer 102 from the platen 112 with lift pins (not shown) and removing the wafer 102 from the platen 112. As known in the art, the voltage applied to the electrodes 114 is different from the voltage directly applied to the wafer 102 to process the wafer 102. For example, in some process, negative voltage is applied to the wafer 102 to attract positively charged ions. To clamp the wafer 102, voltage is applied to the electrodes 114 in the platen 112 to electrostatically clamp the wafer 102 onto the platen 112. As is also known in the art, a dielectric layer is disposed between the electrodes 114 and the wafer 102 to electrically isolate the wafer 102 from the electrodes 114.
The ion 10 directed and implanted into the wafer 102 may be positively charged ions 10. The residual charge in the wafer 102 due to implanting charged ions may cause at a portion of the wafer 102 to stick to the platen 112 surface. Unloading such a wafer 102 may be difficult. Also, if a layer of dielectric film is coated on the lower surface of the wafer 102, the neutralization of the charged ions and electrons may be delayed, thus causing the wafer 102 to remain attached to the platen 112 surface even when the clamping voltage has been removed. Attempting to separate the wafer 102 from the platen 112 surface using excessive force may result in wafer breakage. The wafer breakage may be more frequent if a layer of dielectric film (not shown) is coated on the lower surface of the wafer 102.
As such, a new method of clamping and declamping is needed.